1. Field of the Invention
The present invention relates to a chip package. More particularly, the present invention relates to a wire-through-slot type of chip package.
2. Description of the Related Art
With the rapid development in semiconductor manufacturing techniques in recent years, various high-performance electronic products are introduced, and integrated circuits (IC) with a higher level of integration are produced. Concurrent with the advance in operating speed and function of IC components, the heat generated by the IC units must be rapidly dissipated through proper channels. Otherwise, overheating may cause a temporary or permanent breakdown of the IC devices. Therefore, IC packaging plays a vital role in the IC fabrication process. Because IC devices are generally fabricated on a semiconductor chip before enclosing the semiconductor chip to form a package, this part of the packaging process is often called chip packaging.
In the past, the technique for packaging a dynamic random access memory (DRAM) includes wire bonding. First, the contact points of a chip disposed on a module board are electrically connected to a plurality of contact points (so called gold fingers) on the module board through a plurality of conductive wires. Thereafter, an encapsulant is used to encapsulate the chip and the conductive wires. However, with the increase of the operating speed of the DRAM, the amount of heat generated by the DRAM in operation also increases. To increase the heat-dissipating rate of the DRAM, a micro-ball grid array package (micro-BGA package) has been developed.
FIG. 1 is a schematic cross-sectional view of a conventional micro-ball grid array package. As shown in FIG. 1, the micro-ball grid array package 100 comprises a package substrate 110, a circuit layer 120, a chip 130, a plurality of conductive wires 140, an encapsulant 150, and a plurality of solder balls 160. The package substrate 110 has a first surface 110a, a second surface 110b on the other side of the first surface 110a and a slot 112. The circuit layer 120 is disposed on the first surface 110a and around the slot 112. The chip 130 is disposed on the first surface 110b to cover the slot 112. The chip 130 has a plurality of signal pads 132 and a plurality of non-signal pads 134. The non-signal pads 134 are ground pads or power pads, for example. The slot 112 exposes the signal pads 132 and the non-signal pads 134. Furthermore, the two ends of some of the conductive wires 140 connect the signal pads 132 with the circuit layer 120 while the two ends of other conductive wires 140 connect the non-signal pads 134 with the circuit layer 120.
The encapsulant 150 encapsulates the chip 130, the conductive wires 140 and a portion of the circuit layer 120. The solder balls 160 are disposed on the circuit layer 120 for electrical connection with an external device. It should be noted that the signals from the chip 130 are transmitted to the external device via the signal pads 132, corresponding conductive wires 140, the circuit layer 120 and the solder balls 160. In addition, return current is inputted to the chip 130 via other solder balls 160, the circuit layer 120, corresponding conductive wires 140 and the non-signal pads 134.
Since the return current must travel through the conductive wires 140 of the micro-ball grid array package 100 before returning to the chip, the return loop of the returning current is longer. Furthermore, the conductive wires 140 and the circuit layer 120 of the micro-BGA package 100 are a source of impedance mismatch. Hence, the conventional micro-BGA package 100 has a higher insertion loss and return loss. In addition, the loop inductance also increases when the chip 130 outputs high-frequency signals.